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Required for the Skynet5 SCATS modem project team to provide Firmware engineering effort for SGM Release 2.
Tasks include interpreting subsystem architecture design, definition and design of subsystems, understanding of existing VHDL code and writing new VHDL code to achieve system functionality. Will also be required to define tests, analyse, simulate and confirm subsystem performance in order to verify compliance with specification.
Required to maintain a good working relationship with other parts of the SCATS team, in particular liaison on engineering aspects, to minimise impact of system changes.
Qualifications and/or Skills
Essential:
Technical degree or Diploma with min. 5 years in a responsible engineering role.
Previous Experience
Essential:,
1 2 years VHDL experience, Mentor Graphics HDL Designer , Modelsim, Precision Synthesis
Desirable:
DOORS, Clearcase, Relevant modems experience, Xilinx Devices, Digital Signal Processing functions
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