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We expect that you will have been laying out ASICs (and cells) such as these for at least five years, and ideally for longer. The company’s tool suite is centred on Cadence tools, although tools from other EDA vendors are also used. It would also be advantageous for you to have experience in the use of Verilog (or alternatively VHDL) for simulation and synthesis, and also with HSPICE for transistor-level logic design. To apply contact Scott McMahon in the first instance on 0131 514 5000 or email scott@pulserecruitment.com.
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