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Our client has an opening for a bright, highly skilled, ASIC Layout engineer. You will be implementing the company’s multi-GigaBit Interface Megacell technology in exciting new high-speed applications. As well as providing design services on internal design projects, you will be part of a small team providing Technical Support to our clients Sales Team and to customers throughout the world who will be incorporating this technology into their own ASIC products. We need you to have experience in laying out high speed, transistor-level logic circuits (such as full-custom, mixed signal, and logic library cells) for deep sub-micron ASICs using 0.18um process technologies, or smaller. Clock rates or bandwidths of these designs will have been at multiples of 100MHz or even more than 1GHz. We expect that you will have been laying out ASICs (and cells) such as these for at least five years, and ideally for longer. The company’s tool suite is centred on Cadence tools, although tools from other EDA vendors are also used. It would also be advantageous for you to have experience in the use of Verilog (or alternatively VHDL) for simulation and synthesis, and also with HSPICE for transistor-level logic design. To apply contact Scott McMahon in the first instance on 0131 514 5000 or email scott@pulserecruitment.com.
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