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Software Engineers / EDA with the following mix of skills are currently being recruited for: C, C++, Perl, sh, m4, Verilog, VHDL,CVS, EDA, Software, Parser, compiler, Degree, GUI, UI, User Interface
This is a unique opportunity to get in on the ground floor of a newly funded EDA start-up in Manchester. If you are the right candidate you will be given the chance to make significant contributions to world-class products and to grow your experience and responsibility with the company.
Having just completed their first major release they are now recruiting at least 4 engineers to join their tool development team. Responsibilities will include overseeing and testing the implementation of Verilog front-end, and to provide best-practice lead in simulation model generation.
Candidates will be experienced in the implementation of Verilog/VHDL front ends for simulation systems, netlist parsing / manipulation. Experience in testing of compliance to standards for Verilog/VHDL/SystemC would be a plus.
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